A multi-layer line structure including a plurality of lines provided in a plurality of layers and also including a connection hole provided to connect the plurality of lines located in the plurality of layers is known (see, for example, Japanese Laid-Open Patent Publication No. 2000-150519). In such a multi-layer line structure, an organic resin material such as polyimide or the like is often used as an insulating layer provided between the layers. A reason for this is an organic resin material generally has a low dielectric constant and thus is unlikely to cause delay of a signal transmitted through the lines.
However, an organic resin material has a thermal expansion coefficient that is higher than that of a material of lines, for example, copper or the like. Therefore, when a line structure is subjected to a heat cycle test or used in a high temperature environment, a disconnecting is likely to occur at, for example, a bottom part of the connection hole due to a difference in the thermal expansion coefficient between the resin material and the lines.
This will be described specifically. The thermal expansion coefficient (linear expansion coefficient) of an organic material is 50 to 100 E-6/K. In the case where copper (Cu) is used as a material of a line, the thermal expansion coefficient (linear expansion coefficient) of the material of the line is 17 E-6/K. As can be seen, the thermal expansion coefficient of the organic material is several times as high as the thermal expansion coefficient of the material of the line. In the case where the line structure during production is exposed to an atmosphere exceeding, for example, 200° C., a tensile stress is caused to copper in the connection hole. The tensile stress is caused because the thermal expansion of the organic resin material acts to increase a distance between the lines above and below the organic resin material.
As a result, copper in the connection hole moves in order to alleviate the tensile stress, which forms voids at the bottom part of the connection hole. The voids cause a flaw in electric connection between the upper and lower lines.
There are other flaws in addition to the formation of the voids. Since the adhesive force between a barrier conductive layer covering the bottom part and a side surface of the connection hole, and the organic resin, is low, the barrier conductive layer is deformed and is peeled off from the organic resin.
In general, a multi-layer line structure in a printed circuit board, an interposer or the like is assumed to be used in an environment in which the temperature is changed in cycles from −25° C. to 125° C. The temperature change cycle in such an environment also causes a strong tensile stress to the copper in the connection hole, which also causes a flaw in electric connection as described above.
Recently, LSIs are reduced in size and increased in integration degree, and along with this, LSI chips tend to be mounted on more printed circuit boards and more interposers. In such a situation, there is an increasing demand for a higher density of line layers in a multi-layer line structure.
In order to realize such a high density, it is necessary to decrease the width of the lines, the interval between the lines, and the size of the connection hole. In addition, a structure called a “stacked via”, in which another connection hole is stacked on the copper in the connection hole, is needed. This structure further increases the tensile stress of the copper in the connection hole, and thus raises the ratio of connection flaws. This decreases the reliability.
The present invention has an object of providing a multi-layer line structure or the like which decreases the occurrence of a disconnecting at, for example, a bottom part of a connection hole.
The tensile stress can be slightly decreased by decreasing the height of the connection hole. However, this decreases the distance between the upper and lower line layers, and thus increases the parasitic capacitance and causes crosstalk and signal propagation delay. This makes it difficult to allow the performance of LSIs mounted on printed circuit boards or interposers to be fully exhibited.
The present invention has another object of providing a multi-layer line structure or the like which suppresses the increase of parasitic capacitance and the occurrence of crosstalk and signal propagation delay as compared with a conventional multi-layer line structure even though the distance between the upper and lower line layers is decreased.
When the height of the connection hole is decreased, the effect of an additive (leveler) in an electrolytic plating solution cannot be fully exhibited for filing the connection hole with copper by electrolytic plating. Therefore, the connection hole is not fully filled with copper. As a result, voids are formed in the connection hole, which decreases the reliability, like the voids formed at the bottom part of the connection hole.
The present invention has still another object of providing a multi-layer line structure or the like which suppresses the formation of voids in a connection hole.
In a conventional multi-layer line structure in which an organic resin film is used as an insulating film provided between the copper lines, the organic resin film is in direct contact with outer circumferential surfaces of the copper lines except for the bottom part of the copper lines. Therefore, each time a heat treatment is performed, copper atoms are thermally diffused into the organic resin film around the copper lines. Also, an electric field caused between adjacent lines ionizes and diffuses the copper atoms. Such diffusion decreases the distance between the line layers. This state causes a problem that shortcircuit between the line layers and electrical breakdown of the organic resin film are likely to occur.
Regarding the structure of an LSI, Cu lines are formed by a Damascene process. According to the Damascene process, a barrier metal is located on side surfaces and bottom edges of the Cu lines in order to suppress diffusion of the Cu atoms. However, a material usable for the barrier metal, namely, a material containing Ti or Ta has a high electric resistance. Therefore, there is a problem that as the thickness of the barrier metal is larger with respect to the width of the lines, the resistance of the lines is increased.